Hysteresis and turn-on voltage tailoring of indium gallium zinc oxide transistors by employing a sandwiched structure with indium oxide

Jae-Yun Lee+, Gergely Tarsoly+, Suchang Yoo+, Fei Shan, Heung Gyoon Ryu, Seungkeun Choi, Yong Jin Jeong and Sung-Jin Kim

+Equal contribution

Materials Letters 2022 322 132504. DOI: 10.1016/j.matlet.2022.132504


Transparent electronics with low power consumption is an important area of research for the display industry. Operating voltages of transistors can be successfully reduced by employing gate dielectrics with high dielectric constants. However, interfacial trap sites between dielectric and semiconductor layers might cause hysteresis. Here, transistors were fabricated using amorphous indium gallium zinc oxide (a-IGZO, molar ratio of In:Ga:Zn 1:1:1), a transparent semiconductor with high electron mobility. When prepared on top of Al2O3 gate dielectric, drain current was found to depend on the direction of the gate sweep. A stacked active layer was prepared with the a-IGZO being sandwiched between In2O3 thin films to mitigate the hysteresis of the device. Moreover, it was found that by varying the In2O3 layer thickness, the device fabrication can be optimized to improve the device-to-device reproducibility of the charge carrier mobility. Additionally, the turn-on voltage, a crucial parameter of transistors in binary logic circuits, improved significantly when using the optimized layer structure.